NEPTUNE FPGA Control

Justin Reed

The -10kV DC backbone power cable for the NEPTUNE project creates a grid over the western Pacific Ocean, and at each of the ~40 nodes in that cable is a Branching Unit (BU). The basic schematic of the BU is illustrated below in Figure 1. It is the BU's job to maintain the integrity of the backbone system by automatically identifying and isolating faults in the cable. It achieves this by opening and closing the switches seen in Figure 1. The controller uses the current and voltage measurements (as indicated) to determine the switching actions on the backbone cable and spur cable. The FPGA Control is implemented as the central digital logic in the BU, backing up the analog BU controllers.

Figure 1: Basic function of Branch Units

Basic BU Operation

In the event of a cable fault, the power system promptly shuts down and restarts. The backbone voltage at this time is +500V. During this period, known as T1, all switches are closed. The backbone voltage then swings to -500V, triggering the FPGA.

Upon being triggered, the FPGA enters a time delay T2. This delay is fixed in length and allows the shore power station to perform fault analysis. Since the Science Node is not yet turned on, the presence of current in the spur cable indicates a cable fault and the spur cable switch is opened. The FPGA then enters time delay T3.

Unlike T2, T3 is variable in length and is computed by multiplying the backbone voltage by a constant. Since cable faults effectively ground the entire cable, the BUs nearest the fault will have the lowest voltage, and will thus have the shortest T3. At the end of T3, if the backbone current has not decreased significantly, the backbone switch opens.

After all switching is complete, the backbone voltage is ramped up to -10kV.

FPGA Design

The FPGA is based on a Moore Finite State Machine (FSM) written in Verilog. To simplify its construction and debugging, its many functions are split into modules that interact with one another. At the core is the FSM, connected to several modules. A simplified illustration is seen below in Figure 2. The Time Delay T3 and Backbone Current modules are the most complex because they control data input and processing, while the others perform much simpler tasks.

Figure 2: Basic FPGA Module Layout

FPGA Hardware Testing

After testing in software simulations using Mentor Graphics' Modelsim software simulation program, testing is done at the hardware level. This is accomplished with a prototyping board from Actel that employs a 208-pin APA075 Pro ASICPLUS FLASH-based FPGA. This is a perfect testing platform for this project because it is fully reprogrammable, is a similar architecture to the target chip, and has plenty of I/O channels for debugging. Its photo is seen in Figure 3 below.

Figure 3: FPGA Testing Board

Acknowledgements

Thanks go out to those who have helped me, financially or otherwise, on this project. This includes (but is certainly not limited to):